| 1 | Design and analysis of low power phase locked loop with multiple output using VLSI technology | |
| Researcher: | Belorkar, Ujwala A | |
| Guide: | Ladhake, Siddharth A | |
| University: | Sant Gadge Baba Amravati University | |
| Language: | English | |
| Shodhganga | ||
| 2 | Design and performance evaluation of multistage interconnection networks | |
| Researcher: | Rinkle Rani | |
| Guide: | Kaur, Lakhwinder | |
| University: | Punjabi University | |
| Language: | English | |
| Shodhganga | ||