| Type of Material: | Thesis |
| Title: | Design and analysis of low power phase locked loop with multiple output using VLSI technology |
| Researcher: | Belorkar, Ujwala A |
| Guide: | Ladhake, Siddharth A |
| Department: | Department of Engineering and Technology |
| Publisher: | Sant Gadge Baba Amravati University |
| Place: | Amravati |
| Year: | 2010 |
| Language: | English |
| Subject: | Vlsi technology | Computer science |
| Dissertation/Thesis Note: | PhD |
| Fulltext: | Shodhganga |
| 000 | 00000ntm a2200000ua 4500 | |
| 001 | 262884 | |
| 003 | IN-AhILN | |
| 005 | 2013-12-05 08:44:58 | |
| 008 | __ | 121205t2010||||ii#||||g|m||||||||||eng|| |
| 035 | __ | |a(IN-AhILN)th_262884 |
| 040 | __ | |aAMRV_444602|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aBelorkar, Ujwala A|eResearcher |
| 110 | __ | |aDepartment of Engineering and Technology|bSant Gadge Baba Amravati University|dAmravati |
| 245 | __ | |aDesign and analysis of low power phase locked loop with multiple output using VLSI technology |
| 260 | __ | |aAmravati|bSant Gadge Baba Amravati University|c2010 |
| 502 | __ | |bPhD |
| 518 | __ | |oDate of Notification|d2010 |
| 653 | __ | |aVlsi technology |
| 653 | __ | |aComputer science |
| 700 | __ | |aLadhake, Siddharth A|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/5393|yShodhganga |
| 905 | __ | |anotification |
User Feedback Comes Under This section.