| 1 | Area and power efficient double output architecture for signed and modulo multiplier | |
| Researcher: | Rosi, A. | |
| Guide: | Seshasayanan, R. | |
| University: | Anna University | |
| Language: | English | |
| Shodhganga | ||
| 2 | Synthesis and implementation of evolvable arithmetic IP cores for reconfigurable hardware | |
| Researcher: | Kunaraj, K. | |
| Guide: | Seshasayanan, R. | |
| University: | Anna University | |
| Language: | English | |
| Shodhganga | ||
| 3 | ||
| Researcher: | Vino Vilmet Rose, A. | |
| Guide: | Seshasayanan, R. | |
| University: | Anna University | |
| Language: | English | |
| Shodhganga | ||
| 4 | Low power delay and high precision log based floating point unit for image compression | |
| Researcher: | Vaithiyanathan, D. | |
| Guide: | Seshasayanan, R. | |
| University: | Anna University | |
| Language: | English | |
| Shodhganga | ||