| Type of Material: | Thesis |
| Title: | Synthesis and implementation of evolvable arithmetic IP cores for reconfigurable hardware |
| Researcher: | Kunaraj, K. |
| Guide: | Seshasayanan, R. |
| Publisher: | Anna University |
| Place: | Chennai |
| Language: | English |
| Dissertation/Thesis Note: | PhD |
| Fulltext: | Shodhganga |
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| 005 | 2018-08-14 08:47:53 | |
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| 100 | __ | |aKunaraj, K.|eResearcher |
| 245 | __ | |aSynthesis and implementation of evolvable arithmetic IP cores for reconfigurable hardware |
| 260 | __ | |aChennai|bAnna University |
| 502 | __ | |bPhD |
| 700 | __ | |aSeshasayanan, R.|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/141619|yShodhganga |
| 905 | __ | |anotification |
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