| 1 | Test pattern compression for low power system on chip soc design testing | |
| Researcher: | Saravana, S | |
| Guide: | Har Narayan Upadhyay | |
| University: | SASTRA University | |
| Language: | English | |
| Shodhganga | ||
| 2 | ||
| Researcher: | Balaji, V | |
| Guide: | Har Narayan Upadhyay | |
| University: | SASTRA University | |
| Language: | English | |
| Shodhganga | ||