| Type of Material: | Thesis |
| Title: | Test pattern compression for low power system on chip soc design testing |
| Researcher: | Saravana, S |
| Guide: | Har Narayan Upadhyay |
| Publisher: | SASTRA University |
| Place: | Thanjavur |
| Language: | English |
| Dissertation/Thesis Note: | PhD |
| Fulltext: | Shodhganga |
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| 001 | 337899 | |
| 003 | IN-AhILN | |
| 005 | 2018-08-14 05:32:55 | |
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| 035 | __ | |a(IN-AhILN)th_337899 |
| 040 | __ | |aSRAT_613402|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aSaravana, S|eResearcher |
| 245 | __ | |aTest pattern compression for low power system on chip soc design testing |
| 260 | __ | |aThanjavur|bSASTRA University |
| 502 | __ | |bPhD |
| 700 | __ | |aHar Narayan Upadhyay|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/90055|yShodhganga |
| 905 | __ | |anotification |
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