IndCat

1	Design and synthesis of efficient MAC architectures for high speed decimal processor
Researcher:	James, Rekha K
Guide:	Jacob, K Poulose
University:	Cochin University of Science and Technology
Language:	English
Shodhganga
2	An efficient explicit congestion reduction in high traffic high speed networks through automated rate controlling
Researcher:	Reddy, K Satyanarayan
Guide:	Reddy, Lokanatha C
University:	Dravidian University
Language:	Arabic
Shodhganga
3	An efficient explicit congestion reduction in high traffic high speed networks through automated rate controlling
Researcher:	Reddy, K Satyanarayan
Guide:	Reddy, Lokanatha C
University:	Dravidian University
Language:	Arabic
Shodhganga