Title : Design and synthesis of efficient MAC architectures for high speed decimal processor

Type of Material: Thesis
Title: Design and synthesis of efficient MAC architectures for high speed decimal processor
Researcher: James, Rekha K
Guide: Jacob, K Poulose
Department: Department of Computer Science
Publisher: Cochin University of Science and Technology
Place: Cochin
Year: 04/01/2010
Language: English
Subject: Computer sciences
High speed decimal processor
Dissertation/Thesis Note: PhD
Fulltext: Shodhganga

00000000ntm a2200000ua 4500
001258551
003IN-AhILN
0052013-12-04 12:42:59
008__130507t2010||||ii#||||g|m||||||||||eng||
035__|a(IN-AhILN)th_258551
040__|aCUST_682022|dIN-AhILN
041__|aeng
100__|aJames, Rekha K|eResearcher
110__|aDepartment of Computer Science|bCochin University of Science and Technology|dCochin
245__|aDesign and synthesis of efficient MAC architectures for high speed decimal processor
260__|aCochin|bCochin University of Science and Technology|c04/01/2010
502__|bPhD
518__|oDate of Notification|d2010-01-04
653__|aComputer sciences
653__|aHigh speed decimal processor
700__|aJacob, K Poulose|eGuide
856__|uhttp://shodhganga.inflibnet.ac.in/handle/10603/8623|yShodhganga
905__|anotification

User Feedback Comes Under This section.