| Type of Material: | Thesis |
| Title: | Development of a CMoS analog gate array with a few extended simulation studies |
| Researcher: | Singh, Rajinder |
| Guide: | Bhattacharyya, A B | Nagchaudhuri, D |
| Department: | Department of Electrical Engineering |
| Publisher: | Indian Institute of Technology-Delhi |
| Place: | New Delhi |
| Year: | 1991 |
| Language: | English |
| Subject: | Engineering | Electronics Engineering | Design | Triode Ion Plating Systems | Discharge | Electrical Engineering |
| Dissertation/Thesis Note: | PhD |
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| 001 | 6281 | |
| 003 | IN-AhILN | |
| 005 | 2011-01-13 00:00:00 | |
| 008 | __ | 911231t1991||||ii#||||g|m||||||||||eng|| |
| 035 | __ | |a(IN-AhILN)th_6281 |
| 040 | __ | |aIITD_110016|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aSingh, Rajinder|eResearcher |
| 110 | __ | |aDepartment of Electrical Engineering|bIndian Institute of Technology-Delhi|dNew Delhi|eIn |
| 245 | __ | |aDevelopment of a CMoS analog gate array with a few extended simulation studies |
| 260 | __ | |aNew Delhi|bIndian Institute of Technology-Delhi|c1991 |
| 502 | __ | |bPhD |
| 650 | __ | |aElectrical Engineering|2UGC |
| 653 | __ | |aEngineering |
| 653 | __ | |aElectronics Engineering |
| 653 | __ | |aDesign |
| 653 | __ | |aTriode Ion Plating Systems |
| 653 | __ | |aDischarge |
| 700 | __ | |aBhattacharyya, A B|eGuide |
| 700 | __ | |aNagchaudhuri, D|eGuide |
| 905 | __ | |anotification |
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