| Type of Material: | Thesis |
| Title: | Intelligent Reconfigurable Audio Processor Design with Reconfigurable on Chip Communication Wrapper Module |
| Researcher: | BEULAH HEMALATHA, S |
| Guide: | VIGNESWARAN, T |
| Department: | Department of Electronics and Communication Engineering |
| Publisher: | Bharath University, Chennai |
| Place: | Chennai |
| Year: | 2018 |
| Language: | English |
| Subject: | Engineering | Engineering and Technology | Engineering Electrical and Electronic | Electrical Engineering | Engineering and Technology |
| Dissertation/Thesis Note: | PhD; Department of Electronics and Communication Engineering, Bharath University, Chennai, Chennai; 2018; D13EC009 |
| Fulltext: | Shodhganga |
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| 040 | __ | |aBHAU_600073|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aBEULAH HEMALATHA, S|eResearcher |
| 110 | __ | |aDepartment of Electronics and Communication Engineering|bBharath University, Chennai|dChennai|ein |
| 245 | __ | |aIntelligent Reconfigurable Audio Processor Design with Reconfigurable on Chip Communication Wrapper Module |
| 260 | __ | |aChennai|bBharath University, Chennai|c2018 |
| 300 | __ | |dDVD |
| 502 | __ | |bPhD|cDepartment of Electronics and Communication Engineering, Bharath University, Chennai, Chennai|d2018|oD13EC009 |
| 520 | __ | |aWith the increase in the heterogeneous components in a Multi Processor System on chip, intercommunication between the different IP cores or blocks in a SoC turns out to be a problem. The Proposed architecture helps to use the resources efficiently through runtime reconfiguration of the communication channel as per the communication requirements. This reconfigurable NoC architecture could be the solution for growing communication demands, Quality of service, decreased silicon rate and network scalability. This research work focuses on the design of a Reconfigurable Communication Wrapper that allows easy communication between the heterogeneous IP cores. The efficiency of the proposed wrapper based on chip communication link is improved through optimization using Genetic Algorithm. A Reconfigurable Audio Processor has been implemented as an application to prove the performance of the proposed reconfigurable communication wrapper. Reconfigurable audio processor is one which has a capability of reconfiguring the |
| 650 | __ | |aElectrical Engineering|2UGC |
| 650 | __ | |aEngineering and Technology|2AIU |
| 653 | __ | |aEngineering |
| 653 | __ | |aEngineering and Technology |
| 653 | __ | |aEngineering Electrical and Electronic |
| 700 | __ | |aVIGNESWARAN, T|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/314301|yShodhganga |
| 905 | __ | |afromsg |
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