| Type of Material: | Thesis |
| Title: | Design and Analysis of 4 Bit Sram Ternary Logic using CNTFET |
| Researcher: | TAMIL SELVAN, S |
| Guide: | SUNDARARAJAN, M |
| Department: | Department of Electronics and Communication Engineering |
| Publisher: | Bharath University, Chennai |
| Place: | Chennai |
| Year: | 2020 |
| Language: | English |
| Subject: | Engineering | Engineering and Technology | Engineering Electrical and Electronic | Electrical Engineering | Engineering and Technology |
| Dissertation/Thesis Note: | PhD; Department of Electronics and Communication Engineering, Bharath University, Chennai, Chennai; 2020; D13EC011 |
| Fulltext: | Shodhganga |
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| 003 | IN-AhILN | |
| 005 | 2024-09-18 16:29:00 | |
| 008 | __ | 240918t2020||||ii#||||g|m||||||||||eng|| |
| 035 | __ | |a(IN-AhILN)th_454734 |
| 040 | __ | |aBHAU_600073|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aTAMIL SELVAN, S|eResearcher |
| 110 | __ | |aDepartment of Electronics and Communication Engineering|bBharath University, Chennai|dChennai|ein |
| 245 | __ | |aDesign and Analysis of 4 Bit Sram Ternary Logic using CNTFET |
| 260 | __ | |aChennai|bBharath University, Chennai|c2020 |
| 300 | __ | |dDVD |
| 502 | __ | |bPhD|cDepartment of Electronics and Communication Engineering, Bharath University, Chennai, Chennai|d2020|oD13EC011 |
| 520 | __ | |aDesign of 3VL memory portable usage of CNTFET. 3VL is a capable opportunity to standard binary common sense, as it has better overall concert in terms of place, energy and additionally decreases intersect postpone. The planned ternary memory cellular realizes a significant saving in vicinity as related with existing layout for the reason that and#955; policies are one of a kind for CNTFET. In addition to that, this bankruptcy is to extend CNFETs based SRAM and implement it right into a VHDLAMS. To acquire this purpose, a compact model of the transistor known as enhancement mode MOSFET-like SWCNT-CNFET is used. This circuitwell matched model of CNFET is described using VHDL-AMS and examined for simple electric uniqueness. This model is valid for CNFETs with channel lengths extra than 20nm. Based on the CNFETs a new SRAM is designed, and carried out in VHDL-AMS. The overall performance of the proposed SRAM mobile is investigated and in comparison with SRAMs from conventional MOSFETs. The effect of substrate b |
| 650 | __ | |aElectrical Engineering|2UGC |
| 650 | __ | |aEngineering and Technology|2AIU |
| 653 | __ | |aEngineering |
| 653 | __ | |aEngineering and Technology |
| 653 | __ | |aEngineering Electrical and Electronic |
| 700 | __ | |aSUNDARARAJAN, M|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/313967|yShodhganga |
| 905 | __ | |afromsg |
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