| Type of Material: | Thesis |
| Title: | Performance Improvement of Certain Multiprocessor System on Chip for Low Power Applications |
| Researcher: | KARTHICK, R |
| Guide: | SUNDARARAJAN, M |
| Department: | Department of Electronics and Communication Engineering |
| Publisher: | Bharath University, Chennai |
| Place: | Chennai |
| Year: | 2018 |
| Language: | English |
| Subject: | Engineering | Engineering and Technology | Engineering Electrical and Electronic | Electrical Engineering | Engineering and Technology |
| Dissertation/Thesis Note: | PhD; Department of Electronics and Communication Engineering, Bharath University, Chennai, Chennai; 2018; D13EC002 |
| Fulltext: | Shodhganga |
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| 040 | __ | |aBHAU_600073|dIN-AhILN |
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| 100 | __ | |aKARTHICK, R|eResearcher |
| 110 | __ | |aDepartment of Electronics and Communication Engineering|bBharath University, Chennai|dChennai|ein |
| 245 | __ | |aPerformance Improvement of Certain Multiprocessor System on Chip for Low Power Applications |
| 260 | __ | |aChennai|bBharath University, Chennai|c2018 |
| 300 | __ | |dDVD |
| 502 | __ | |bPhD|cDepartment of Electronics and Communication Engineering, Bharath University, Chennai, Chennai|d2018|oD13EC002 |
| 520 | __ | |aIn order to cope up with the functional operation criteria, our work concentrate on the percentage of indefinite values in the tests performed. A low power broadside test set is shown from a functional broadside set with the derivation of slanted load test cubes in BIST circuits. The twin effect of programmable truncated multiplication and fault-tolerant Digital Signal Processing (DSP) design is put on to reduce voltage beyond critical timing level. Effectiveness modulations possessions of truncated multiplication are examined for the betterment of fault tolerant designs, ranging the system operating voltage range and minimizing error correction burden. The lower power test schemes along with advanced Razor technique is implemented with the original Digital signal Processing. This work reflects the combined design of pre-coding, bit loading and receives filters for a MIMO wireless communication system. Together the sender and the receiver are supposed to match the frequency matrix exactly. It is already kno |
| 650 | __ | |aElectrical Engineering|2UGC |
| 650 | __ | |aEngineering and Technology|2AIU |
| 653 | __ | |aEngineering |
| 653 | __ | |aEngineering and Technology |
| 653 | __ | |aEngineering Electrical and Electronic |
| 700 | __ | |aSUNDARARAJAN, M|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/313703|yShodhganga |
| 905 | __ | |afromsg |
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