| Type of Material: | Thesis |
| Title: | An Efficient High Speed Hierarchical Topology for Network on Chip Design of Mega Cmp Core Architecture Fractal Cone Topology |
| Researcher: | KULKARNI RASHMI MANIK |
| Guide: | ARULSELVI, S |
| Department: | Department of Electronics and Communication Engineering |
| Publisher: | Bharath University, Chennai |
| Place: | Chennai |
| Year: | 2020 |
| Language: | English |
| Subject: | Engineering | Engineering and Technology | Engineering Electrical and Electronic | Electrical Engineering | Engineering and Technology |
| Dissertation/Thesis Note: | PhD; Department of Electronics and Communication Engineering, Bharath University, Chennai, Chennai; 2020; D14EC508 |
| Fulltext: | Shodhganga |
| 000 | 00000ntm a2200000ua 4500 | |
| 001 | 454680 | |
| 003 | IN-AhILN | |
| 005 | 2024-09-18 12:12:38 | |
| 008 | __ | 240918t2020||||ii#||||g|m||||||||||eng|| |
| 035 | __ | |a(IN-AhILN)th_454680 |
| 040 | __ | |aBHAU_600073|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aKULKARNI RASHMI MANIK|eResearcher |
| 110 | __ | |aDepartment of Electronics and Communication Engineering|bBharath University, Chennai|dChennai|ein |
| 245 | __ | |aAn Efficient High Speed Hierarchical Topology for Network on Chip Design of Mega Cmp Core Architecture Fractal Cone Topology |
| 260 | __ | |aChennai|bBharath University, Chennai|c2020 |
| 300 | __ | |dDVD |
| 502 | __ | |bPhD|cDepartment of Electronics and Communication Engineering, Bharath University, Chennai, Chennai|d2020|oD14EC508 |
| 520 | __ | |aHigh performance embedded applications are developed using system-on-chips (SoCs) which includes silicon intensive, integrated application processors sequentially. These SoCs integrate multi-core processor (i.e., ARM Cortex9 or A15) with variety of memory interface controllers, communication interface controllers and special purpose accelerators. Traditionally bus matrix is used for integrating these intellectual property cores (IPs). Bus based architectures are not scalable and consume more area and power, which has fueled design of network on chip (NoC). In this research work, a methodology for customized NoC architecture is introduced considering various aspects of NoC as well as the SoC. Policies for optimizing bandwidth requirement, size of the IP (area or gate count), IP location for optimum path lengths are conversed for competence which forms the methodology for optimum NoC consecutively. As IPs in SoC increase in numbers, NoC for interconnecting every IP may result in over networking. For closely c |
| 650 | __ | |aElectrical Engineering|2UGC |
| 650 | __ | |aEngineering and Technology|2AIU |
| 653 | __ | |aEngineering |
| 653 | __ | |aEngineering and Technology |
| 653 | __ | |aEngineering Electrical and Electronic |
| 700 | __ | |aARULSELVI, S|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/310441|yShodhganga |
| 905 | __ | |afromsg |
User Feedback Comes Under This section.