Title : Design of Symmetric and Asymmetric Multilevel Inverter Topology with different Pulse Width Modulation Scheme

Type of Material: Thesis
Title: Design of Symmetric and Asymmetric Multilevel Inverter Topology with different Pulse Width Modulation Scheme
Researcher: RAJNISH KUMAR SHARMA
Guide: IRUSAPPARAJAN, G
Department: Department of Engineering and Technology(Electrical Engineering)
Publisher: Bharath University, Chennai
Place: Chennai
Year: 2020
Language: English
Subject: Engineering
Engineering and Technology
Engineering Electrical and Electronic
Electrical Engineering
Engineering and Technology
Dissertation/Thesis Note: PhD; Department of Engineering and Technology(Electrical Engineering), Bharath University, Chennai, Chennai; 2020; D14EE005
Fulltext: Shodhganga

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