Title : Design of Symmetric and Asymmetric Multilevel Inverter Topology with different Pulse Width Modulation Scheme

Type of Material: Thesis
Title: Design of Symmetric and Asymmetric Multilevel Inverter Topology with different Pulse Width Modulation Scheme
Researcher: RAJNISH KUMAR SHARMA
Guide: IRUSAPPARAJAN, G
Department: Department of Engineering and Technology(Electrical Engineering)
Publisher: Bharath University, Chennai
Place: Chennai
Year: 2020
Language: English
Subject: Engineering
Engineering and Technology
Engineering Electrical and Electronic
Electrical Engineering
Engineering and Technology
Dissertation/Thesis Note: PhD; Department of Engineering and Technology(Electrical Engineering), Bharath University, Chennai, Chennai; 2020; D14EE005
Fulltext: Shodhganga

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035__|a(IN-AhILN)th_454631
040__|aBHAU_600073|dIN-AhILN
041__|aeng
100__|aRAJNISH KUMAR SHARMA|eResearcher
110__|aDepartment of Engineering and Technology(Electrical Engineering)|bBharath University, Chennai|dChennai|ein
245__|aDesign of Symmetric and Asymmetric Multilevel Inverter Topology with different Pulse Width Modulation Scheme
260__|aChennai|bBharath University, Chennai|c2020
300__|dDVD
502__|bPhD|cDepartment of Engineering and Technology(Electrical Engineering), Bharath University, Chennai, Chennai|d2020|oD14EE005
520__|aMultilevel inverter technology for average and higher power industrialized applications has become popular in recent years. Cascaded Half Bridge, Neutral spot Clamped and Flying Capacitor are three primary multilevel inverters topography. Cascaded Half Bridge has become popular for its modular nature, easy control, durability, availability and lack of problem with capacitor imbalance. Over traditional 2-level inverters, these inverters put forward some inherent reward. One of the main advantages is the excellent of the ac output voltage of the multilevel inverters. New symmetric and asymmetric multilevel inverter topologies are suggested in this research. In this investigation we concentrate on this topology which is series relation of several Half-Bridge cells with even and imbalanced magnitude of dc sources recognized as symmetric and asymmetric arrangement. The appearance of preferred topologies is evaluated on the basis of the three significant performance (performance) indexes that are fundamental comp
650__|aElectrical Engineering|2UGC
650__|aEngineering and Technology|2AIU
653__|aEngineering
653__|aEngineering and Technology
653__|aEngineering Electrical and Electronic
700__|aIRUSAPPARAJAN, G|eGuide
856__|uhttp://shodhganga.inflibnet.ac.in/handle/10603/309720|yShodhganga
905__|afromsg

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