| Type of Material: | Thesis |
| Title: | EVOLUTIONARY ALGORITHMICAL APPROACH FOR VLSI PHYSICAL DESIGN |
| Researcher: | VARATHARAJAN R |
| Guide: | S. PERUMAL SANKAR |
| Department: | Department of Electronics and Communication Engineering |
| Publisher: | Bharath University, Chennai |
| Place: | Chennai |
| Year: | 2011 |
| Language: | English |
| Subject: | SEQUENTIAL GLOBAL ROUTING | PERFORMANCE DRIVEN GLOBAL ROUTING | MODULE INTERCHANGE BASED METHODS | SIMULATED ANNEALING | Electrical Engineering | Engineering and Technology |
| Dissertation/Thesis Note: | PhD; Department of Electronics and Communication Engineering, Bharath University, Chennai, Chennai; 2011; D08EC003 |
| Fulltext: | Shodhganga |
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| 040 | __ | |aBHAU_600073|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aVARATHARAJAN R|eResearcher |
| 110 | __ | |aDepartment of Electronics and Communication Engineering|bBharath University, Chennai|dChennai|ein |
| 245 | __ | |aEVOLUTIONARY ALGORITHMICAL APPROACH FOR VLSI PHYSICAL DESIGN |
| 260 | __ | |aChennai|bBharath University, Chennai|c2011 |
| 300 | __ | |dDVD |
| 502 | __ | |bPhD|d2011|oD08EC003|cDepartment of Electronics and Communication Engineering, Bharath University, Chennai, Chennai |
| 518 | __ | |d2008-01-01|oDate of Registration |
| 520 | __ | |aThe task of VLSI physical design is to produce the layout of an integrated circuit. The layout problem in VLSI-design can be broken up into the subtasks partitioning, floor planning, placement and routing. Physical design is the process of determining the physical location of active devices and interconnecting them inside the boundary of the VLSI chip the earliest and the most critical stage in VLSI layout design is the placement. The background is the rectangle packing problem: given a set of rectangular modules of arbitrary sizes, place them without overlap on a plane within a rectangle of minimum area. The VLSI placement problem is to place the object in the fixed area of die with out overlap and with some cost constrain. Such as the wire length and area of the die. The wire length and the area optimization is the major task in the physical design. We first introduced about the major technique involved in the algorithm.Next,Routing can be classified into two types. One is Global routing and another one i |
| 650 | __ | |aElectrical Engineering|2UGC |
| 650 | __ | |aEngineering and Technology|2AIU |
| 653 | __ | |aSEQUENTIAL GLOBAL ROUTING |
| 653 | __ | |aPERFORMANCE DRIVEN GLOBAL ROUTING |
| 653 | __ | |aMODULE INTERCHANGE BASED METHODS |
| 653 | __ | |aSIMULATED ANNEALING |
| 700 | __ | |aS. PERUMAL SANKAR|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/170918|yShodhganga |
| 905 | __ | |afromsg |
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