| Type of Material: | Thesis |
| Title: | Embedded data acquisition hardware for high speed satellite data archival and processing |
| Researcher: | Prasad G. |
| Guide: | Vasantha N. |
| Department: | Department of Electronics and Communication Engineering |
| Publisher: | Jawaharlal Nehru Technological University, Hyderabad |
| Place: | Hyderabad |
| Year: | 2016 |
| Language: | English |
| Subject: | Engineering | Engineering and Technology | Engineering Electrical and Electronic | Satellite data | Electronics and Communication Engineering | Engineering and Technology |
| Dissertation/Thesis Note: | PhD; Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Hyderabad, Hyderabad; 2016 |
| Fulltext: | Shodhganga |
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| 040 | __ | |aJNTU_500028|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aPrasad G.|eResearcher |
| 110 | __ | |aDepartment of Electronics and Communication Engineering|bJawaharlal Nehru Technological University, Hyderabad|dHyderabad|ein|0U-0017 |
| 245 | __ | |aEmbedded data acquisition hardware for high speed satellite data archival and processing |
| 260 | __ | |c2016|aHyderabad|bJawaharlal Nehru Technological University, Hyderabad |
| 300 | __ | |dDVD|a215p. |
| 502 | __ | |bPhD|cDepartment of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Hyderabad, Hyderabad|d2016 |
| 518 | __ | |oDate of Award|dJuly 2016 |
| 518 | __ | |oDate of Registration|d2009-01-01 |
| 520 | __ | |aTo design an effectively fast and reliable high performance platform for satellite real time data acquisition, archiving and processing. A data acquisition system on a Programmable chip using the latest state of art technology FPGA, FIFO s and PCI-X 64bit/66MHz Master core is to be designed for acquiring multiple channel data from remote sensing satellites and can be interfaced to a true 64bit server for data archival and processing.It is planned to be designed for operating at frequencies ranging from 5MHz/sec to 200MHz/sec per channel. A short form standard Printer circuit Board adds on card is planned. Electrical inputs to the hardware are planned through Low voltage Differential Signaling. The power for the card will be drawn from the host system through PCI-X bus. The Embedded Data Acquisition Hardware is planned with PCI-X 64bit /66MHz DMA Interface to support both input channels in interleaved method. Data Acquisition board with Plug and Play features in PCI systems is planned. Frame Synchronization |
| 650 | __ | |aElectronics and Communication Engineering|2UGC |
| 650 | __ | |aEngineering and Technology|2AIU |
| 653 | __ | |aEngineering |
| 653 | __ | |aEngineering and Technology |
| 653 | __ | |aEngineering Electrical and Electronic |
| 653 | __ | |aSatellite data |
| 700 | __ | |aVasantha N.|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/298455|yShodhganga |
| 905 | __ | |afromsg |
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