| Type of Material: | Thesis |
| Title: | Studies on Design and Implementation of 10-Bit, 50 Ms/Sec Pipelined Analog to Digital Converter |
| Researcher: | Rao, P Prasada |
| Guide: | Kishore, K Lal |
| Department: | Department of Electronics and Communication Engineering |
| Publisher: | Jawaharlal Nehru Technological University, Hyderabad |
| Place: | Hyderabad |
| Year: | 2013 |
| Language: | English |
| Subject: | Analog | Design | Digital | Pipelined | Studies | Electronics and Communication Engineering | Engineering and Technology |
| Dissertation/Thesis Note: | PhD; Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Hyderabad, Hyderabad; 2013 |
| Fulltext: | Shodhganga |
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| 008 | __ | 240705t2013||||ii#||||g|m||||||||||eng|| |
| 035 | __ | |a(IN-AhILN)th_453920 |
| 040 | __ | |aJNTU_500028|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aRao, P Prasada|eResearcher |
| 110 | __ | |aDepartment of Electronics and Communication Engineering|bJawaharlal Nehru Technological University, Hyderabad|dHyderabad|ein|0U-0017 |
| 245 | __ | |aStudies on Design and Implementation of 10-Bit, 50 Ms/Sec Pipelined Analog to Digital Converter |
| 260 | __ | |aHyderabad|bJawaharlal Nehru Technological University, Hyderabad|c2013 |
| 300 | __ | |c-|dNone|a177 p. |
| 500 | __ | |aReferences p. 146-161 appendixp. 162-177 |
| 502 | __ | |bPhD|cDepartment of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Hyderabad, Hyderabad|d2013 |
| 520 | __ | |aAll electrical signals in nature are analog and since most of the signal processing is done in the digital domain, Analog to Digital (ADC) and Digital to Analog (DAC) converters have become a necessity. Flash ADC makes all bit decisions in a single go while Successive newlineapproximation ADC makes single bit decision at a time. Flash ADCs are faster but area increases exponentially with bit length while successive approximation ADC is slow and occupies less area. Between these two newlineextremes, many other architectures exist, deciding a fixed number of bits at a time such as pipelined and multistep ADCs. They balance circuit complexity and speed. For medium speed and with high resolution, pipelined ADCs are promising. newline |
| 650 | __ | |aElectronics and Communication Engineering|2UGC |
| 650 | __ | |aEngineering and Technology|2AIU |
| 653 | __ | |aAnalog |
| 653 | __ | |aDesign |
| 653 | __ | |aDigital |
| 653 | __ | |aPipelined |
| 653 | __ | |aStudies |
| 700 | __ | |eGuide|aKishore, K Lal |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/19321|yShodhganga |
| 905 | __ | |afromsg |
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