| Type of Material: | Thesis |
| Title: | Studies on high performance CMOS circuits in DSM Technology using Domino logic |
| Researcher: | Govindarajulu, Salendra |
| Guide: | Prasad, T. Jayachandra |
| Department: | Department of Electronics and Communication Engineering |
| Publisher: | Jawaharlal Nehru Technological University, Hyderabad |
| Place: | Hyderabad |
| Year: | 2013 |
| Language: | English |
| Subject: | Circuits | Domino | Performance | Technology | Electronics and Communication Engineering | Engineering and Technology |
| Dissertation/Thesis Note: | PhD; Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Hyderabad, Hyderabad; 2013 |
| Fulltext: | Shodhganga |
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| 040 | __ | |aJNTU_500028|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aGovindarajulu, Salendra|eResearcher |
| 110 | __ | |aDepartment of Electronics and Communication Engineering|bJawaharlal Nehru Technological University, Hyderabad|dHyderabad|ein|0U-0017 |
| 245 | __ | |aStudies on high performance CMOS circuits in DSM Technology using Domino logic |
| 260 | __ | |aHyderabad|bJawaharlal Nehru Technological University, Hyderabad|c2013 |
| 300 | __ | |a219 p.|dNone|c- |
| 500 | __ | |aReferences p. 205-219 |
| 502 | __ | |cDepartment of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Hyderabad, Hyderabad|d2013|bPhD |
| 520 | __ | |aDynamic logic circuits have been popularly used in advanced high speed processors as they occupy less area and have higher speed in comparison with the static CMOS counterparts. Domino logic is one of newlinethe popular dynamic logic. The major problems with domino gates are higher dynamic power, static power and lower noise immunity than newlinestatic logic circuits. In this work, an attempt has been made to design novel circuit techniques for robust, energy-efficient and high performance domino logic circuits in deep submicron technology. This work has been divided into three parts. In the first part, various novel energy-efficient, high performance domino logic circuit techniques have been developed and implemented. Performance design metrics in the presence of leakage currents have been analyzed. The EDP (Energy Delay Product) has been compared with the PDP (Power Delay Product) and a new metric called PEP (Power Energy Product) has been introduced. Comparing these three performance metrics, it has been |
| 650 | __ | |aElectronics and Communication Engineering|2UGC |
| 650 | __ | |aEngineering and Technology|2AIU |
| 653 | __ | |aCircuits |
| 653 | __ | |aDomino |
| 653 | __ | |aPerformance |
| 653 | __ | |aTechnology |
| 700 | __ | |aPrasad, T. Jayachandra|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/18951|yShodhganga |
| 905 | __ | |afromsg |
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