| Type of Material: | Thesis |
| Title: | Complete on chip low voltage low drop out voltage regulator |
| Researcher: | Agarwal, Gopal |
| Guide: | Dwivedi, Ved Vyas |
| Department: | Department of Electronics and Communication Engineering |
| Publisher: | C.U. Shah University |
| Place: | Wadhwan |
| Year: | 2020 |
| Language: | English |
| Subject: | Engineering | chip | Low voltage | Regulator | Electronics and Communication Engineering | Engineering and Technology |
| Dissertation/Thesis Note: | PhD; Department of Electronics and Communication Engineering, C.U. Shah University, Wadhwan; 2020 |
| Fulltext: | Shodhganga |
| 000 | 00000ntm a2200000ua 4500 | |
| 001 | 451984 | |
| 003 | IN-AhILN | |
| 005 | 2024-01-24 15:34:41 | |
| 008 | __ | 240124t2020||||ii#||||g|m||||||||||eng|| |
| 035 | __ | |a(IN-AhILN)th_451984 |
| 040 | __ | |aCUSU_363030|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aAgarwal, Gopal|eResearcher |
| 110 | __ | |aDepartment of Electronics and Communication Engineering|bC.U. Shah University|dWadhwan|ein|0U-0708 |
| 245 | __ | |aComplete on chip low voltage low drop out voltage regulator |
| 260 | __ | |aWadhwan|bC.U. Shah University|c2020 |
| 300 | __ | |a121p.|dCD |
| 502 | __ | |cDepartment of Electronics and Communication Engineering, C.U. Shah University, Wadhwan|d2020|bPhD |
| 518 | __ | |d2020|oDate of Award |
| 518 | __ | |oDate of Registration|d2015 |
| 520 | __ | |aAbstractnewlineDesigning of Low Drop-Out Voltage Regulators (LDO s) operating without a large off-chip capacitor, having a very good transient response and maintaining the loop stability for full load current range in low supply voltage and low quiescent current environment is a challenging task.newlineThe present thesis work proposes a complete on chip low drop-out voltage regulator working in low voltage environment.newlineA voltage reference based on peaking current mirror circuit has been designed for the LDO. The designed voltage reference consumes very low power dissipation and consists of only MOSFET devices in its design.newlineA two stage design for LDO is adopted in this work. Body bias effect is exploited to reduce the size of pass transistor for required amount of load current.newline |
| 650 | __ | |aElectronics and Communication Engineering|2UGC |
| 650 | __ | |aEngineering and Technology|2AIU |
| 653 | __ | |aEngineering |
| 653 | __ | |achip |
| 653 | __ | |aLow voltage |
| 653 | __ | |aRegulator |
| 700 | __ | |eGuide|aDwivedi, Ved Vyas |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/291382|yShodhganga |
| 905 | __ | |afromsg |
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