Title : Design of low power and high speed multiply accumulate unit using enhanced gate diffusion input technique

Type of Material: Thesis
Title: Design of low power and high speed multiply accumulate unit using enhanced gate diffusion input technique
Researcher: Uma, R.
Guide: Dhavachelvan, P.
Department: Department of Computer Science
Publisher: Pondicherry University, Puducherry
Place: Pondicherry
Year: 2015
Language: English
Subject: Low power
High speed
Gate diffusion
Input technique
Accumulate unit
Computer Science and Information Technology
Engineering and Technology
Dissertation/Thesis Note: PhD; Department of Computer Science, Pondicherry University, Puducherry, Pondicherry; 2015
Fulltext: Shodhganga

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035__|a(IN-AhILN)th_448817
040__|aPNDI_605104|dIN-AhILN
041__|aeng
100__|aUma, R.|eResearcher
110__|aDepartment of Computer Science|bPondicherry University, Puducherry|dPondicherry|ein
245__|aDesign of low power and high speed multiply accumulate unit using enhanced gate diffusion input technique
260__|aPondicherry|bPondicherry University, Puducherry|c2015
300__|axviii, 246 p.|dDVD
502__|cDepartment of Computer Science, Pondicherry University, Puducherry, Pondicherry|d2015|bPhD
518__|d2011-11-14|oDate of Registration
650__|aComputer Science and Information Technology|2UGC
650__|aEngineering and Technology|2AIU
653__|aLow power
653__|aHigh speed
653__|aGate diffusion
653__|aInput technique
653__|aAccumulate unit
700__|aDhavachelvan, P.|eGuide
856__|uhttp://shodhganga.inflibnet.ac.in/handle/10603/217714|yShodhganga
905__|afromsg

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