Type of Material: | Thesis |
Title: | Development and implementation of low power methodologies for video codec using FPGA |
Researcher: | C., Karthikeyan |
Guide: | Rangachar, MJS |
Department: | Department of Communication Engineering |
Publisher: | Hindustan Institute of Technology & Science |
Place: | Chennai |
Year: | 2018 |
Language: | English |
Subject: | low power methodologies | video codec |
Dissertation/Thesis Note: | PhD |
000 | 00000ntm a2200000ua 4500 | |
001 | 442717 | |
003 | IN-AhILN | |
005 | 2020-12-29 09:39:08 | |
008 | __ | 201229t2018||||ii#||||g|m||||||||||eng|| |
035 | __ | |a(IN-AhILN)th_442717 |
040 | __ | |aHITS_603103|dIN-AhILN |
041 | __ | |aeng |
100 | __ | |aC., Karthikeyan|eResearcher |
110 | __ | |aDepartment of Communication Engineering|bHindustan Institute of Technology & Science|dChennai |
245 | __ | |aDevelopment and implementation of low power methodologies for video codec using FPGA |
260 | __ | |aChennai|bHindustan Institute of Technology & Science|c2018 |
502 | __ | |bPhD |
653 | __ | |alow power methodologies |
653 | __ | |avideo codec |
700 | __ | |aRangachar, MJS|eGuide |
905 | __ | |anotification |
User Feedback Comes Under This section.