| Type of Material: | Thesis |
| Title: | intergrated approach to partitioning placement wire routing of computer logic circuit |
| Researcher: | Chaudhuri, Parimal Pal |
| Guide: | Chattopadhyay, A K |
| Department: | Department of Electrical Engineering |
| Publisher: | Indian Institute of Technology |
| Place: | Kharagpur |
| Year: | 1979 |
| Language: | English |
| Subject: | Engineering | Electronics Engineering | Computer | Electrical Engineering |
| Dissertation/Thesis Note: | PhD |
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| 001 | 43898 | |
| 003 | IN-AhILN | |
| 005 | 2011-01-13 00:00:00 | |
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| 100 | __ | |aChaudhuri, Parimal Pal|eResearcher |
| 110 | __ | |aDepartment of Electrical Engineering|bIndian Institute of Technology|dKharagpur|eIn |
| 245 | __ | |aintergrated approach to partitioning placement wire routing of computer logic circuit |
| 260 | __ | |aKharagpur|bIndian Institute of Technology|c1979 |
| 502 | __ | |bPhD |
| 650 | __ | |aElectrical Engineering|2UGC |
| 653 | __ | |aEngineering |
| 653 | __ | |aElectronics Engineering |
| 653 | __ | |aComputer |
| 700 | __ | |aChattopadhyay, A K|eGuide |
| 905 | __ | |anotification |
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