Title : An area efficient high speed low power VLSI architecture of discrete cosine transform for signal processing applications

Type of Material: Thesis
Title: An area efficient high speed low power VLSI architecture of discrete cosine transform for signal processing applications
Researcher: M, Thiruveni
Guide: Shanthi, D
Publisher: Anna University
Place: Chennai
Dissertation/Thesis Note: PhD
Fulltext: Shodhganga

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035__|a(IN-AhILN)th_425758
040__|aANNA_600025|dIN-AhILN
041__|aoth
100__|aM, Thiruveni|eResearcher
245__|aAn area efficient high speed low power VLSI architecture of discrete cosine transform for signal processing applications
260__|aChennai|bAnna University
502__|bPhD
700__|aShanthi, D|eGuide
856__|uhttp://shodhganga.inflibnet.ac.in/handle/10603/196057|yShodhganga
905__|anotification

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