| Type of Material: | Thesis |
| Title: | Certain investigations on heuristic optimization techniques for area minimization in fixed outline non slicing voltage island based VLSI floorplanning |
| Researcher: | K, Sivasubramanian |
| Guide: | Jayanthi, K B |
| Publisher: | Anna University |
| Place: | Chennai |
| Dissertation/Thesis Note: | PhD |
| Fulltext: | Shodhganga |
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| 001 | 425687 | |
| 003 | IN-AhILN | |
| 005 | 2018-08-15 12:48:28 | |
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| 035 | __ | |a(IN-AhILN)th_425687 |
| 040 | __ | |aANNA_600025|dIN-AhILN |
| 041 | __ | |aoth |
| 100 | __ | |aK, Sivasubramanian|eResearcher |
| 245 | __ | |aCertain investigations on heuristic optimization techniques for area minimization in fixed outline non slicing voltage island based VLSI floorplanning |
| 260 | __ | |aChennai|bAnna University |
| 502 | __ | |bPhD |
| 700 | __ | |aJayanthi, K B|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/195986|yShodhganga |
| 905 | __ | |anotification |
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