| Type of Material: | Thesis |
| Title: | Power minimization in arithmetic logic unit design using clock gating techniques for high speed circuits |
| Researcher: | L, Raja |
| Guide: | Thanushkodi, K |
| Publisher: | Anna University |
| Place: | Chennai |
| Dissertation/Thesis Note: | PhD |
| Fulltext: | Shodhganga |
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| 001 | 425439 | |
| 003 | IN-AhILN | |
| 005 | 2018-08-15 12:47:32 | |
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| 035 | __ | |a(IN-AhILN)th_425439 |
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| 100 | __ | |aL, Raja|eResearcher |
| 245 | __ | |aPower minimization in arithmetic logic unit design using clock gating techniques for high speed circuits |
| 260 | __ | |aChennai|bAnna University |
| 502 | __ | |bPhD |
| 700 | __ | |aThanushkodi, K|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/195725|yShodhganga |
| 905 | __ | |anotification |
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