| Type of Material: | Thesis |
| Title: | Hierarchical evolution of digital arithmetic circuits with built in self test logic for delay faults |
| Researcher: | V P Kolanchinathan |
| Publisher: | St. Peters University |
| Place: | Chennai |
| Language: | English |
| Dissertation/Thesis Note: | PhD |
| Fulltext: | Shodhganga |
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| 001 | 413119 | |
| 003 | IN-AhILN | |
| 005 | 2018-08-14 11:44:04 | |
| 008 | __ | 180814t####||||ii#||||g|m||||||||||eng|| |
| 035 | __ | |a(IN-AhILN)th_413119 |
| 040 | __ | |aSTPU_600054|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aV P Kolanchinathan|eResearcher |
| 245 | __ | |aHierarchical evolution of digital arithmetic circuits with built in self test logic for delay faults |
| 260 | __ | |aChennai|bSt. Peters University |
| 502 | __ | |bPhD |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/180775|yShodhganga |
| 905 | __ | |anotification |
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