| Type of Material: | Thesis |
| Title: | efficient implementation of AES using FPGA for high secure computing |
| Researcher: | Senthil Kumar M |
| Guide: | Rajalakshmi, S |
| Publisher: | Sri Chandrasekharendra Saraswathi Viswa Mahavidyalaya |
| Place: | Kanchipuram |
| Language: | English |
| Dissertation/Thesis Note: | PhD |
| Fulltext: | Shodhganga |
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| 001 | 386273 | |
| 003 | IN-AhILN | |
| 005 | 2018-08-14 09:15:27 | |
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| 035 | __ | |a(IN-AhILN)th_386273 |
| 040 | __ | |aCSMK_631561|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aSenthil Kumar M|eResearcher |
| 245 | __ | |aefficient implementation of AES using FPGA for high secure computing |
| 260 | __ | |aKanchipuram|bSri Chandrasekharendra Saraswathi Viswa Mahavidyalaya |
| 502 | __ | |bPhD |
| 520 | __ | |aFile attached |
| 700 | __ | |aRajalakshmi, S|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/148501|yShodhganga |
| 905 | __ | |anotification |
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