| Type of Material: | Thesis |
| Title: | OSynthesis and simulationf novel multi valued logic processor architecture |
| Researcher: | Narkhede Satish Sudhakar |
| Guide: | Chaudhari, B. S.and Kharate |
| Publisher: | Savitribai Phule Pune University |
| Place: | Pune |
| Language: | English |
| Dissertation/Thesis Note: | PhD |
| Fulltext: | Shodhganga |
| 000 | 00000ntm a2200000ua 4500 | |
| 001 | 361217 | |
| 003 | IN-AhILN | |
| 005 | 2018-08-14 07:15:45 | |
| 008 | __ | 180814t####||||ii#||||g|m||||||||||eng|| |
| 035 | __ | |a(IN-AhILN)th_361217 |
| 040 | __ | |aPUNE_411007|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aNarkhede Satish Sudhakar|eResearcher |
| 245 | __ | |aOSynthesis and simulationf novel multi valued logic processor architecture |
| 260 | __ | |aPune|bSavitribai Phule Pune University |
| 502 | __ | |bPhD |
| 700 | __ | |aChaudhari, B. S.and Kharate|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/118240|yShodhganga |
| 905 | __ | |anotification |
User Feedback Comes Under This section.