| Type of Material: | Thesis |
| Title: | Design of Architecture and FPGA Implementation of Video Encoder with Rate Control |
| Researcher: | VENUGOPAL N |
| Guide: | Dr S. Ramachandran |
| Publisher: | Dr. M.G.R. Educational and Research Institute |
| Place: | Chennai |
| Language: | English |
| Dissertation/Thesis Note: | PhD |
| Fulltext: | Shodhganga |
| 000 | 00000ntm a2200000ua 4500 | |
| 001 | 357814 | |
| 003 | IN-AhILN | |
| 005 | 2018-08-14 07:01:29 | |
| 008 | __ | 180814t####||||ii#||||g|m||||||||||eng|| |
| 035 | __ | |a(IN-AhILN)th_357814 |
| 040 | __ | |aDMGR_600095|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aVENUGOPAL N|eResearcher |
| 245 | __ | |aDesign of Architecture and FPGA Implementation of Video Encoder with Rate Control |
| 260 | __ | |aChennai|bDr. M.G.R. Educational and Research Institute |
| 502 | __ | |bPhD |
| 700 | __ | |aDr S. Ramachandran|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/114154|yShodhganga |
| 905 | __ | |anotification |
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