| Type of Material: | Thesis |
| Title: | Development of new algorithms for test generation and simulation of stuck at faults in logic circuits |
| Researcher: | Bhuvaneswari, M C |
| Guide: | Sivanandam, S N |
| Publisher: | Bharathiar University |
| Place: | Coimbatore |
| Language: | English |
| Dissertation/Thesis Note: | PhD |
| Fulltext: | Shodhganga |
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| 100 | __ | |aBhuvaneswari, M C|eResearcher |
| 245 | __ | |aDevelopment of new algorithms for test generation and simulation of stuck at faults in logic circuits |
| 260 | __ | |aCoimbatore|bBharathiar University |
| 502 | __ | |bPhD |
| 700 | __ | |aSivanandam, S N|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/108818|yShodhganga |
| 905 | __ | |anotification |
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