| Type of Material: | Thesis |
| Title: | Design validation and FPGA implementation of multistage telecommunication networks in HDL environment |
| Researcher: | Kumar, Adesh |
| Guide: | Kuchhal, Piyush and Singhal |
| Publisher: | University of Petroleum and Energy Studies (UPES) |
| Place: | Dehradun |
| Language: | English |
| Dissertation/Thesis Note: | PhD |
| Fulltext: | Shodhganga |
| 000 | 00000ntm a2200000ua 4500 | |
| 001 | 323548 | |
| 003 | IN-AhILN | |
| 005 | 2018-08-14 04:27:22 | |
| 008 | __ | 180814t####||||ii#||||g|m||||||||||eng|| |
| 035 | __ | |a(IN-AhILN)th_323548 |
| 040 | __ | |aUPES_248007|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aKumar, Adesh|eResearcher |
| 245 | __ | |aDesign validation and FPGA implementation of multistage telecommunication networks in HDL environment |
| 260 | __ | |aDehradun|bUniversity of Petroleum and Energy Studies (UPES) |
| 502 | __ | |bPhD |
| 700 | __ | |aKuchhal, Piyush and Singhal|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/72468|yShodhganga |
| 905 | __ | |anotification |
User Feedback Comes Under This section.