| Type of Material: | Thesis |
| Title: | Studies on the synthesis of district logic circuits using threshold gates and MOS networks |
| Researcher: | Pal, Ajit |
| Department: | Department of Electrical Engineering |
| Publisher: | University of Calcutta |
| Place: | Calcutta |
| Year: | 1976 |
| Language: | English |
| Subject: | Engineering | Electrical Engineering | Transmission | Electrical Engineering |
| Dissertation/Thesis Note: | PhD |
| 000 | 00000ntm a2200000ua 4500 | |
| 001 | 27997 | |
| 003 | IN-AhILN | |
| 005 | 2011-01-13 00:00:00 | |
| 008 | __ | 761231t1976||||ii#||||g|m||||||||||eng|| |
| 035 | __ | |a(IN-AhILN)th_27997 |
| 040 | __ | |aCLCT_700073|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aPal, Ajit|eResearcher |
| 110 | __ | |aDepartment of Electrical Engineering|bUniversity of Calcutta|dCalcutta|eIn |
| 245 | __ | |aStudies on the synthesis of district logic circuits using threshold gates and MOS networks |
| 260 | __ | |aCalcutta|bUniversity of Calcutta|c1976 |
| 502 | __ | |bPhD |
| 650 | __ | |aElectrical Engineering|2UGC |
| 653 | __ | |aEngineering |
| 653 | __ | |aElectrical Engineering |
| 653 | __ | |aTransmission |
| 905 | __ | |anotification |
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