Type of Material: | Thesis |
Title: | Algorithm and architecture design of DDS synthesizers for improved performance of PLL |
Researcher: | Patel, Govind Singh |
Guide: | Sharma, Sanjay |
Department: | Department of Electronics & Communication Engineering |
Publisher: | Thapar University, Patiala |
Place: | Patiala |
Year: | 2016 |
Language: | English |
Subject: | Electronics engineering | Communication engineering |
Dissertation/Thesis Note: | PhD |
000 | 00000ntm a2200000ua 4500 | |
001 | 270528 | |
003 | IN-AhILN | |
005 | 2016-03-21 12:00:10 | |
008 | __ | 160321t2016||||ii#||||g|m||||||||||eng|| |
035 | __ | |a(IN-AhILN)th_270528 |
040 | __ | |aTIET_147001|dIN-AhILN |
041 | __ | |aeng |
100 | __ | |aPatel, Govind Singh|eResearcher |
110 | __ | |aDepartment of Electronics & Communication Engineering|bThapar University, Patiala|dPatiala |
245 | __ | |aAlgorithm and architecture design of DDS synthesizers for improved performance of PLL |
260 | __ | |aPatiala|bThapar University, Patiala|c2016 |
502 | __ | |bPhD |
518 | __ | |oDate of Notification|d2016 |
653 | __ | |aElectronics engineering |
653 | __ | |aCommunication engineering |
700 | __ | |aSharma, Sanjay|eGuide |
905 | __ | |anotification |
User Feedback Comes Under This section.