Title : Algorithm and architecture design of DDS synthesizers for improved performance of PLL

Type of Material: Thesis
Title: Algorithm and architecture design of DDS synthesizers for improved performance of PLL
Researcher: Patel, Govind Singh
Guide: Sharma, Sanjay
Department: Department of Electronics & Communication Engineering
Publisher: Thapar University, Patiala
Place: Patiala
Year: 2016
Language: English
Subject: Electronics engineering
Communication engineering
Dissertation/Thesis Note: PhD

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035__|a(IN-AhILN)th_270528
040__|aTIET_147001|dIN-AhILN
041__|aeng
100__|aPatel, Govind Singh|eResearcher
110__|aDepartment of Electronics & Communication Engineering|bThapar University, Patiala|dPatiala
245__|aAlgorithm and architecture design of DDS synthesizers for improved performance of PLL
260__|aPatiala|bThapar University, Patiala|c2016
502__|bPhD
518__|oDate of Notification|d2016
653__|aElectronics engineering
653__|aCommunication engineering
700__|aSharma, Sanjay|eGuide
905__|anotification

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