| Type of Material: | Thesis |
| Title: | VLSI design of low power digital FIR filter using PSPICE and VLSI design of high speed digital FIR filter using VERILOG HDL |
| Researcher: | Vigneswaran T |
| Guide: | Malarvizhi, S |
| Department: | Department of Electronics and Communication Engineering |
| Publisher: | SRM University |
| Place: | Kattankulathur |
| Year: | November, 2008 |
| Language: | English |
| Subject: | Electronics and communication | Vlsi | Pspice | Verilog hdl | Electronics and Communication Engineering |
| Dissertation/Thesis Note: | PhD |
| Fulltext: | Shodhganga |
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| 001 | 263331 | |
| 003 | IN-AhILN | |
| 005 | 2013-12-05 09:37:28 | |
| 008 | __ | 130118t2023||||ii#||||g|m||||||||||eng|| |
| 035 | __ | |a(IN-AhILN)th_263331 |
| 040 | __ | |aSRMI_600033|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aVigneswaran T|eResearcher |
| 110 | __ | |aDepartment of Electronics and Communication Engineering|bSRM University|dKattankulathur |
| 245 | __ | |aVLSI design of low power digital FIR filter using PSPICE and VLSI design of high speed digital FIR filter using VERILOG HDL |
| 260 | __ | |aKattankulathur|bSRM University|cNovember, 2008 |
| 502 | __ | |bPhD |
| 518 | __ | |oDate of Notification|d2008-11 |
| 520 | __ | |aIncluded |
| 650 | __ | |aElectronics and Communication Engineering|2UGC |
| 653 | __ | |aElectronics and communication |
| 653 | __ | |aVlsi |
| 653 | __ | |aPspice |
| 653 | __ | |aVerilog hdl |
| 700 | __ | |aMalarvizhi, S|eGuide |
| 856 | __ | |uhttp://shodhganga.inflibnet.ac.in/handle/10603/6521|yShodhganga |
| 905 | __ | |anotification |
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