| Type of Material: | Thesis |
| Title: | Design and simulation of nanoscale tunneling field effect transistors for cmos application |
| Researcher: | Sneh, Saurabh |
| Guide: | Kumar, Jagadesh |
| Department: | Department of Electical Engineering |
| Publisher: | Indian Institute of Technology Delhi |
| Place: | Delhi |
| Year: | 2009 |
| Language: | English |
| Subject: | Electrical engineering | Cmos application | Nanoscale tunneling |
| Dissertation/Thesis Note: | PhD |
| 000 | 00000ntm a2200000ua 4500 | |
| 001 | 246748 | |
| 003 | IN-AhILN | |
| 005 | 2012-06-26 03:54:12 | |
| 008 | __ | 120626t2009||||ii#||||g|m||||||||||eng|| |
| 035 | __ | |a(IN-AhILN)th_246748 |
| 040 | __ | |aIITD_110016|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aSneh, Saurabh|eResearcher |
| 110 | __ | |aDepartment of Electical Engineering|bIndian Institute of Technology Delhi|dDelhi |
| 245 | __ | |aDesign and simulation of nanoscale tunneling field effect transistors for cmos application |
| 260 | __ | |aDelhi|bIndian Institute of Technology Delhi|c2009 |
| 502 | __ | |bPhD |
| 653 | __ | |aElectrical engineering |
| 653 | __ | |aCmos application |
| 653 | __ | |aNanoscale tunneling |
| 700 | __ | |aKumar, Jagadesh|eGuide |
| 905 | __ | |anotification |
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