| Type of Material: | Thesis |
| Title: | Framework for verification of processor architecture |
| Researcher: | Shah, Asheesh |
| Guide: | Ramani, A K |
| Department: | Department of Computer Engineering |
| Publisher: | Devi Ahilya Vishwavidyalaya |
| Place: | Indore |
| Year: | 2011 |
| Language: | English |
| Subject: | Computer Science |
| Dissertation/Thesis Note: | PhD |
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| 001 | 242272 | |
| 003 | IN-AhILN | |
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| 041 | __ | |aeng |
| 100 | __ | |aShah, Asheesh|eResearcher |
| 110 | __ | |aDepartment of Computer Engineering|bDevi Ahilya Vishwavidyalaya|dIndore |
| 245 | __ | |aFramework for verification of processor architecture |
| 260 | __ | |aIndore|bDevi Ahilya Vishwavidyalaya|c2011 |
| 502 | __ | |bPhD |
| 653 | __ | |aComputer Science |
| 700 | __ | |aRamani, A K|eGuide |
| 905 | __ | |anotification |
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