| Type of Material: | Thesis |
| Title: | Dynamically reconfigurable bitparallel pipelined embedded architecture for high speed signal processing |
| Researcher: | Ramadass, N |
| Guide: | Perinbam, J Raja Paul |
| Department: | Department of Information and Communication Engineering |
| Publisher: | Anna University |
| Place: | Chennai |
| Year: | 2009 |
| Language: | English |
| Subject: | Information & Communication Engineering |
| Dissertation/Thesis Note: | PhD |
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| 040 | __ | |aANNA_600025|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aRamadass, N|eResearcher |
| 110 | __ | |aDepartment of Information and Communication Engineering|bAnna University|dChennai |
| 245 | __ | |aDynamically reconfigurable bitparallel pipelined embedded architecture for high speed signal processing |
| 260 | __ | |aChennai|bAnna University|c2009 |
| 502 | __ | |bPhD |
| 653 | __ | |aInformation & Communication Engineering |
| 700 | __ | |aPerinbam, J Raja Paul|eGuide |
| 905 | __ | |anotification |
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