| Type of Material: | Thesis |
| Title: | Some investigations on multilevel closed loop control of time delay systems |
| Researcher: | Shukla, Shailaja |
| Guide: | Permar, K K |
| Department: | Department of Electrical Engineering |
| Publisher: | RAJIV GANDHI PROUDYOGIKI VISHwavidyalaya |
| Place: | Bhopal |
| Year: | 2002 |
| Language: | English |
| Subject: | Engineering Science | Electrical Engineering | Electrical Engineering |
| Accession No: | Vol 41 Issue 07 |
| Dissertation/Thesis Note: | PhD |
| 000 | 00000ntm a2200000ua 4500 | |
| 001 | 14398 | |
| 003 | IN-AhILN | |
| 005 | 2011-01-13 00:00:00 | |
| 008 | __ | 021231t2002||||ii#||||g|m||||||||||eng|| |
| 035 | __ | |a(IN-AhILN)th_14398 |
| 040 | __ | |aRGPV_462036|dIN-AhILN |
| 041 | __ | |aeng |
| 100 | __ | |aShukla, Shailaja|eResearcher |
| 110 | __ | |aDepartment of Electrical Engineering|bRAJIV GANDHI PROUDYOGIKI VISHwavidyalaya|dBhopal|eIn |
| 245 | __ | |aSome investigations on multilevel closed loop control of time delay systems |
| 260 | __ | |aBhopal|bRAJIV GANDHI PROUDYOGIKI VISHwavidyalaya|c2002 |
| 502 | __ | |bPhD |
| 650 | __ | |aElectrical Engineering|2UGC |
| 653 | __ | |aEngineering Science |
| 653 | __ | |aElectrical Engineering |
| 700 | __ | |aPermar, K K|eGuide |
| 852 | __ | |pVol 41 Issue 07 |
| 905 | __ | |anotification |
User Feedback Comes Under This section.