| Type of Material: | Thesis |
| Title: | multilevel associative processor architecture for parallel processing |
| Researcher: | Kumar, Shashi |
| Guide: | Bhatt, P C P | Maheshwari, S N |
| Department: | Department of Electrical Engineering |
| Publisher: | Indian Institute of Technology-delhi |
| Place: | New Delhi |
| Year: | 1985 |
| Language: | English |
| Subject: | Engineering | Electronics Engineering | Computer | Electrical Engineering |
| Dissertation/Thesis Note: | PhD |
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| 001 | 111049 | |
| 003 | IN-AhILN | |
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| 245 | __ | |amultilevel associative processor architecture for parallel processing |
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| 700 | __ | |aBhatt, P C P|eGuide |
| 700 | __ | |aMaheshwari, S N|eGuide |
| 905 | __ | |anotification |
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